The present invention relates generally to address counters and in particular the present invention relates to up/down address counters in memory devices.
Memory applications increasingly require higher speed access, lower voltage, and greater density. Higher density and lower voltages, however, tend to reduce performance in standard random access memory architectures. To achieve faster access times, a burst read mode has been developed. Burst read mode devices offer improvements in speed and performance by reducing sequential read access times to the memory device.
Burst read mode is typically tied to one edge of an input clock signal. The controller or microprocessor supplies only the initial address to the memory device and a counter in the device counts up a predetermined number of addresses from the specified start location.
FIG. 1 illustrates a typical prior art address generator. The generator uses address latches 101-103 that are connected as an asynchronous counter. In an asynchronous read mode, the address latches 101-103 are comprised of two serially connected latches 108 and 109. These are the master latch 108 and the slave latch 109. The three latches 101-103 illustrated in FIG. 1 are substantially similar. Therefore, only a brief description will be given regarding the first address latch 101 that applies to all of the address latches.
When the burst signal 110 is high (i.e., burst read mode disabled), the first transmission gates 105 in each of the address latches are disabled while the other transmission gates 106 are enabled. When the burst mode is disabled, the transmission gates 116, 118, 120, and 122 are disabled. Furthermore, when the burst mode is disabled, the latch circuits 101, 102, and 103 become simple independent address buffers for the address signals connected to A0pad, A1pad, and A2pad since the signal AL 124 is always high when the burst mode is disabled.
When the burst signal BURSt 110 is low (i.e., BURST read mode enabled), the clock signal CLKp 126 is allowed to pass through the NOR gate 128 in inverted form and through the inverter 130 in non-inverted form. By doing so, the first latch circuit 101 becomes a toggle flip-flop (divide-by-2) and its outputs, A0 and A0b, change state at every rising edge of CLKp 126. Similarly, the second latch circuit 102 is a toggle flip-flop using A0 and A0b as clocks. A1 and A1b change state at every rising edge of A0. Similarly, the third latch circuit 103 is a toggle flip-flop. Its outputs, A2 and A2b, change state at every rising edge of A1.
The address generator 100 starts generating addresses from an initial address stored in the counter with the help of signal AL 124. When this signal 124 is high, the address presented at A0pad, A1pad, and A2pad is stored in 101, 102 and 103 respectively. AL 124 is also an input for NOR gate 128 for this operation. After the initial starting address of the counter is stored in 101, 102, and 103, AL changes from high to low and the address generator 100 generates a new address for every CLKp 126 rising edge.
These addresses are labeled as A0, A1, and A2. At every clock cycle of CLKp the address configuration A0, A1, A2, A0b, A1b, and A2b at the output of the address counter 100 increases by one bit.
The output addresses are input to a decoder 112 that generates a word selecting signal W0-W7 depending on the state of the address lines. The W0-W7 signals are input to a multiplexer 114 to select one set of 16 data out lines from the 128 data line input.
The address generator of FIG. 1 has the advantage of being simple but does not work well at high clock speeds during a burst read operation. This is because its total delay from address generating signal, CLKp, to the generated addresses, A0, A1, and A2, is given by the slowest address generated: A2. Given the serial connection of the divide-by-2 units 101-103, the total delay of A2 is a sum of the delay of each of the units 101-103 to CLKp.
An additional problem is that the divide-by-2 units 101-103 produce the non-inverted and inverted address signals (i.e., A0, A0b, A1, A1b, A2, A2b) separated by one gate delay 115. This causes the decoder 112 to select two words for a time equal to that gate delay, thus causing data contention on the output bus. This reduces the burst read speed of the address generator 100.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for faster burst read address generator to increase the burst read speeds in a memory device.
The above-mentioned problems with memory testing and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
The present invention encompasses a symmetrical divide-by-2 circuit comprising a master latch that holds a data signal and is coupled to a dynamic slave latch through a plurality of transmission gates. The dynamic slave latch capacitively stores, for a predetermined time interval, the data signal transferred from the master latch. In one embodiment, this predetermined time interval is one-half clock cycle.
In one embodiment, the symmetrical divide-by-2 circuit can be used in an address generator in a memory device during a burst read operation. Such an embodiment comprises a plurality of address inputs for accepting a burst read start address. A plurality of the symmetrical divide-by-2 circuits are organized in successive stages. A clock generator circuit that has a one-shot circuit generates an address increment/decrement clock to each of the stages such that the burst read start address is either incremented or decremented in response to a polarity signal. The clock generator circuit further generates an enable clock and an inverse enable clock that are coupled to the transmission gates for enabling a transfer of data from the master latch to the slave latch.
Further embodiments of the invention include methods and apparatus of varying scope.